Hardware-in-the-Loop (HIL) Simulations of MW Scale Power - Investigation of HIL Interface Algorithms with an Inductive Type Superconducting Fault Current Limiter

Existence of adequate power hardware-in-the-loop (PHIL) interface algorithms is important to ensure accuracy and stability of PHIL experiments. Developing and testing of such algorithms is even more important at higher power levels since a) inherent latencies in high power PHIL amplifiers are significantly higher than latencies in low power amplifiers and b) risks and cost of damages to devices under test or amplifier due to instabilities caused by inadequate PHIL are higher at higher power levels. This particular effort focused on assessment of accuracy and stability of HIL interface algorithms applied PHIL testing of an inductive type superconducting fault current limiter (FCL) using the 5 MW PHIL test bed at CAPS. A number of interface algorithms have been identified in the literature, such as those described in [1], for example. As preliminary simulations indicated stability issues using the Ideal Transformer Method (ITM), variants of the Damping Impedance Method (DIM) algorithm were explored for application. Thus, this work focused on PHIL testing of the FCL with multiple surrounding systems, operating conditions, and using several different variations of the DIM interface algorithm. As the modified DIM approach seemed to show improvement in performance over the classical DIM approach, it is believed that this may hold the potential for improved accuracy in many cases. However, it was also noted that stability may be an issue with this approach. Filtering of the feedback impedance was used to attempt to develop a compromise between stability and performance. In general, future work should explore ways to better optimize the tradeoff between stability and performance for a given application.

This work on interface algorithms for PHIL is an addition to the submitted ESRDC report in [2].